Saturday, August 24

Microchip enters the memory infrastructure market

SMC 1000 8x25G provides high-memory bandwidth required by the next generation CPUS and SoC for Artificial intelligence (AI) and Machine learning.

Microchip has just announced the Extended Data center product line and joined the memory infrastructure market with the first serial memory controller on the market. The SMC 1000 8x25G model allows the CPU and other compute center SoC to leverage more than four times more memory channels than the parallel-mounted DDR4 DRAM with the same plug-in structure.

The serial memory controllers of Microchip provide higher memory bandwidth and are not dependent on heavy processing platforms with extremely low latency.

When the number of replication processors in the CPU increases, the average memory bandwidth that each processor core can use decreases by the CPU chip, and the SoC can not increase the number of DDR interfaces in parallel on the same chip to meet the needs of the number Higher amount of personnel.

SMC 1000 8x25G interacts with CPUS through an 8-bit (OMI) Open memory interface – including lanes and 25 Gbps bridges to connect to memory through the DDR4 3200 72-bit interface. The result is a significant reduction in the number of pins required by the CPU or SoC master on each DDR3 memory channel, allowing more memory channels to be used while increasing the usable memory bandwidth.

“New memory interface technologies such as the Open Memory Interface (OMI) enable a wide range of SoC applications to support the growing memory requirements of high-performance data center applications. Microchip steps into the memory infrastructure market marking our determination in improving the efficiency and efficiency of data center , “said Pete Hazen, vice president of Business Unit Solutions data Center Microchip said.